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| tm * * * * TE CH T436416C SDRAM FEATURES 3.3V power supply Four banks operation LVTTL compatible with multiplexed address All inputs are sampled at the positive going edge of system clock * DQM for masking * Auto refresh and self refresh * 64ms refresh period * 15.6 us refresh interval. * MRS cycle with address key programs - CAS Latency ( 2 & 3 ) - Burst Length ( 1 , 2 , 4 , 8 & full page) - Burst Type (Sequential & Interleave) * Available package type in 54 pin TSOP(II) * Operating temperature : 0 ~ +70 C 4M x 16 SDRAM 1M x 16bit x 4Banks Synchronous DRAM GRNERAL DESCRIPTION The T436416C is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits , fabricated with high performance CMOS technology . Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ORDERING INFORMATION PART NO. MAX FREQUENCY PACKAGE PIN ARRANGEMENT (Top View) V DD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 5 4 P IN T S O P ( II) ( 4 0 0 m il x 8 7 5 m il) ( 0 .8 m m P IN P IT C H ) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 V ss D Q 15 V SSQ DQ0 V DDQ T436416C-6S T436416C-7S T436416C-6SG T436416C-7SG 166 MHz 143 MHz 166 MHz 143 MHz 54 pin TSOP(II) 54 pin TSOP(II) 54 pin TSOP(II) lead-free 54 pin TSOP(II) lead-free DQ1 DQ2 V SSQ D Q 14 D Q 13 V DDQ DQ3 DQ4 V DDQ D Q 12 D Q 11 V SSQ DQ5 DQ6 V SSQ D Q 10 DQ9 V DDQ DQ7 V DD DQ8 V ss N .C / R F U UDQM CLK CKE N .C A 11 A9 A8 A7 A6 A5 A4 V ss LDQM WE CAS RAS CS A 13 A 12 A 1 0 /A P A0 A1 A2 A3 V DD TM Technology Inc. reserves the right P. 1 to change products or specifications without notice. Publication Date: AUG. 2004 Revision: A tm TE CH T436416C BLOCK DIAGRAM I/O Control LW E Bank Select D ata Input R egister LD Q M 1M x 16 1M x 16 1M x 16 1M x 16 Row Decoder Row Buffeer Refresh Counter Sense AM P Output Buffer D Qi Address Register C LK A DD LCBR LRAS Col. Buffer C olum n D ecoder Latency & Burst Length LC K E LR A S LC BR LW E LC A S Tim ing Register Program m ing R egister LW C BR LD Q M C LK C KE CS R AS C AS WE L(U)D QM TM Technology Inc. reserves the right P. 2 to change products or specifications without notice. Publication Date: AUG. 2004 Revision: A tm PIN CLK TE CH T436416C PIN DESCRIPTION NAME System Clock Chip Select INPUT FUNCTION Active on the positive going edge to sample all input. Disables or enables device operation by masking or enabling all input except CLK,CKE and L(U)DQM Masks system clock to freeze operation from the next clock cycle. CS CKE Clock Enable CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. A0 ~ A11 A12 ~ A13 Address Bank Select Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11,column address : CA0 ~ CA7 Selects bank to be activated during row address latch time. Select bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK RAS Row Address Strobe with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK CAS Column Address Strobe with CAS low. Enables column access . WE L(U)DQM DQ0 ~ DQ15 VDD/VSS VDDQ/VSSQ Write Enable Data Input/Output Mask Data Input/Output Enables write operation and row precharge. Latches data in starting from CAS , WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when L(U)DQM active. Data inputs/outputs are multiplexed on the same pins. Power Supply/Ground Power and ground for the input buffers and the core logic. Data Output Power/Ground No Connection/Reserved for Future Use Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device. N.C/RFU TM Technology Inc. reserves the right P. 3 to change products or specifications without notice. Publication Date: AUG. 2004 Revision: A tm Parameter TE CH T436416C ABSOLUTE MAXIMUM RATINGS Symbol VIN,VOUT VDD,VDDQ Iout PD TOPR Tstg Value -1.0 to 4.6 -1.0 to 4.6 50 1 0 to +70 -55 to +150 Unit V V mA W C C Voltage on Any Pin Relative To Vss Supply Voltage Relative To Vss Short circuit Output Current Power Dissipation Operating Temperature Storage Temperature Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (TA = 0 to +70C, Voltage referenced to VSS=0V) Parameter Supply Voltage Input High Voltage Input Low Voltage Output logic high voltage Output logic low voltage Input leakage current Output leakage current Symbol VDD,VDDQ VIH VIL VOH VOL IIL IOL Min. 3.0 2.0 -0.3 2.4 -5 -5 Typ 3.3 3.0 0 Max. 3.6 VDD+0.3V 0.8 0.4 5 5 Unit V V V V V uA uA 1 2 IOH=-2mA IOL=2mA 3 4 Notes Note : 1. VIH (max) = 4.6V AC for pulse width 10ns acceptable. 2. VIL (min) = -1.5V AC for pulse width 10ns acceptable. 3. Any input 0V VIN VDD+ 0.3V , all other pin are not under test = 0V. 4. Dout = disable, 0V VOUT VDD . CAPACITANCE (TA =25C,VDD=3.3V, f = 1MHz) Pin CLOCK ADDRESS DQ0 ~ DQ15 RAS,CAS,WE,CS,CKE,LDQM, UDQM Symbol CCLK CADD COUT CIN Min 2.0 2.0 2.0 2.0 Max 4.0 4.0 4.0 5.0 Unit pF pF pF pF TM Technology Inc. reserves the right P. 4 to change products or specifications without notice. Publication Date: AUG. 2004 Revision: A tm TE CH T436416C DC CHARACTERISTICS TA = 0 to 70C , VIH(min)/VIL(max)=2.0V/0.8V Parameter Operating Current ( One Bank Active) Symbol ICC1 Speed version -6 110 2 1 20 -7 100 mA Burst Length = 1 Unit Test Condition Note tRCtRC(min) ,tCCtCC(min),IOL= 0 mA CKE VIL(max),tCC= 1,2 Precharge Standby ICC2P Current in powerICC2PS down mode Precharge Standby ICC2N Current in non power-down mode ICC2NS Active Standby ICC3P Current in powerICC3PS down mode Active Standby ICC3N Current in non power-down mode (One Bank Active) ICC3NS Operating Current (Burst Mode) Refresh Current Self refresh Current ICC4 150 150 ICC5 ICC6 180 tCC (min) mA CKE VIL(max),CLK VIL(max), tCC = 2 CKE VIH(min), CS VIH(min), tCC= tCC (min) mA Input signals are changed one time during 2CLK 2 CKEVIH(min),CLK VIL(min),tCC= Input signals are stable CKE VIL(max),tCC= CKE VIL(max),CLK 15 10 10 30 mA 25 140 140 180 1 tCC (min) mA VIL(max),tCC= tCC (min) 2 CKEVIH(min), CS VIH(min),tCC= Input signals are changed one time during 2CLK CKEVIH(min),CLK VIL(min),tCC= Input signals are stable CAS Latency 3 IOL=0 mA,Page Burst All Band Activated CAS Latency 2 2 mA mA tRC tRC(min) mA CKE 0.2V 1,2 tCCD= tCCD(min) 2 Note: 1. Measured with output open. Addresses are changed one time during 2CLKS . 2. tCC : Clock cycle time. tRC : Row cycle time. tCCD : Column address to column address delay time. TM Technology Inc. reserves the right P. 5 to change products or specifications without notice. Publication Date: AUG. 2004 Revision: A tm TE CH T436416C AC OPERATING CONDITIONS (VDD=3.3V 0.3V ,TA= 0 to 70C) Parameter Input levels (VIH/VIL) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value 2.4 / 0.4 1.4 Unit V V ns V tr / tf = 1 / 1 1.4 See Fig.2 3.3V Output 1200 ohm Output 870 ohm 30pf VOH(DC)=2.4,IOH=-2mA VOL(DC)=0.4,IOL=2mA ZO=50 ohm Vtt=1.4v 50 ohm 30pf (Fig.1) DC Output Load Circuit (Fig.2)AC Output Load Circuit TM Technology Inc. reserves the right P. 6 to change products or specifications without notice. Publication Date: AUG. 2004 Revision: A tm TE CH T436416C OPERATING AC PARAMETER (AC opterating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time (operating) Row cycle time (auto refresh) Last data in to new col. Address delay Last data in to row precharge Last data in to burst stop Col. Address to col. Address delay Number of valid output data Symbol Speed Version -6 -7 12 18 18 40 100K 58 60 1 2 1 1 2 1 63 70 14 20 20 42 Unit ns ns ns ns ns ns ns CLK CLK CLK CLK ea Note 1 1 1 1 1 1,5 2 2 2 3 4 tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRFC(min) tCDL(min) tRDL(min) tBDL(min) tCCD(min) CAS latency=3 CAS latency=2 Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. A new command may be given tRFC after self refresh exit. TM Technology Inc. reserves the right P. 7 to change products or specifications without notice. Publication Date: AUG. 2004 Revision: A tm TE CH T436416C AC CHARACTERISTICS (AC opterating conditions unless otherwise noted) Parameter CAS Latency = 3 CLK cycle time CAS Latency = 2 CLK to valid Output delay Output data hold time CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CAS Latency = 3 CLK to output in Hi-Z CAS Latency = 2 CAS Latency = 3 CAS Latency = 2 Symbol Min -6 Max Min -7 Max Unit Note 1K ns 1 6 1K 7 10 tCC tSAC tOH tCH tCL tSS tSH tSLZ tSHZ 8 2.5 2.5 2.5 1.5 1 0 5.5 6 5.5 6 2.5 2.5 2.5 1.5 1 0 - 6 6 ns 1 ns ns ns ns ns ns ns 2 3 3 3 3 2 6 6 ns ns Note: 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf)=1ns. If tr & tf is longer than 1ns,transient time compensation should be considered, i.e.,[(tr+tf)/2-1]ns should be added to the parameter. TM Technology Inc. reserves the right P.8 to change products or specifications without notice. Publication Date: AUG. 2004 Revision: A tm TE CH T436416C (Unit : number of clock) CAS Latency 3 3 3 2 2 FREQUENCY vs. AC PARAMETER RELATIONAHIP TABLE T436416C-6S Frequency 166MHz(6.0ns) 143MHz(7.0ns) 133MHz(7.5ns) 125MHz(8.0ns) 100MHz(10.0ns) tRC 58ns 10 9 8 8 6 tRAS 40ns 7 6 6 5 4 tRP 18ns 3 3 3 3 2 tRRD 12ns 2 2 2 2 2 tRCD 18ns 3 3 3 3 2 tCCD 6ns 1 1 1 1 1 tCDL 6ns 1 1 1 1 1 tRDL 12ns 2 2 2 2 2 T436416C-7S Frequency 143MHz(7.0ns) 133MHz(7.5ns) 125MHz(8.0ns) 100MHz(10.0ns) 83MHz(12.0ns) (Unit : number of clock) CAS Latency 3 3 3 2 2 tRC 63ns 9 9 8 7 6 tRAS 42ns 6 6 6 5 4 tRP 20ns 3 3 3 2 2 tRRD 14ns 2 2 2 2 2 tRCD 20ns 3 3 3 2 2 tCCD 7ns 1 1 1 1 1 tCDL 7ns 1 1 1 1 1 tRDL 14ns 2 2 2 2 2 Note : 1. Clock count formula : clock base value (round off whole number). clock period TM Technology Inc. reserves the right P.9 to change products or specifications without notice. Publication Date: AUG. 2004 Revision: A tm Address Function TE CH T436416C MODE REGISTER Register Programmed with MRS A13~A12 RFU A11~A10/AP RFU A9 RF U A8 A7 TM A6 A5 A4 A3 BT A2 A1 A0 CAS Latency Burst Length A8 0 0 1 1 Test Mode A7 Type Mode Register Set 0 1 Reserved 0 Reserved 1 Reserved A6 0 0 0 0 1 1 1 1 CAS Latency A5 A4 Latency 0 0 Reserved 0 1 Reserved 1 0 2 1 1 3 0 0 Reserved 0 1 Reserved 1 0 Reserved 1 1 Reserved A3 0 1 Burst Type Type Sequential Interleave A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 Burst Length A0 BT=0 BT=1 0 1 1 1 2 2 0 4 4 1 8 8 0 Reserved Reserved 1 Reserved Reserved 0 Reserved Reserved 1 Full Page Reserved Full Page Length : 256 Note : 1. RFU (reserved for future use) should stay "0" during MRS cycle. 2. Test mode use A7~A8, vendor specific options use A9, A10~A11 and A12~A13. A7~A8, A10 /AP~A11 and A12~A13 must be set to low for normal SDRAM operation. Refer to the table for specific codes for various burst length, burst type and CAS latencies. Mode Register Write Timing CLOCK CKE CS RAS CAS WE A 0 -A 1 3 TM Technology Inc. reserves the right P.10 to change products or specifications without notice. Publication Date: AUG. 2004 Revision: A tm TE CH T436416C Burst Length and Sequence (Burst of Two) Starting Address (column address A0 binary) Sequential Addressing Sequence (decimal) Interleave Addressing Sequence (Decimal) 0 1 (Burst of Four) Starting Address (column address A1-A0 binary) 0,1 1,0 0,1 1,0 Sequential Addressing Sequence (decimal) Interleave Addressing Sequence (Decimal) 00 01 10 11 (Burst of Eight) Starting Address (column address A2-A0 binary) 0,1,2,3 1,2,3,0 2,3,0,1 3,0,1,2 0,1,2,3 1,0,3,2 2,3,0,1 3,2,1,0 Sequential Addressing Sequence (decimal) Interleave Addressing Sequence (Decimal) 000 001 010 011 100 101 110 111 4Mx16 divice. 0,1,2,3,4,5,6,7 1,2,3,4,5,6,7,0 2,3,4,5,6,7,0,1 3,4,5,6,7,0,1,2 4,5,6,7,0,1,2,3 5,6,7,0,1,2,3,4 6,7,0,1,2,3,4,5 7,0,1,2,3,4,5,6 0,1,2,3,4,5,6,7 1,0,3,2,5,4,7,6 2,3,0,1,6,7,4,5 3,2,1,0,7,6,5,4 4,5,6,7,0,1,2,3 5,4,7,6,1,0,3,2 6,7,4,5,2,3,0,1 7,6,5,4,3,2,1,0 Full page burst is an extension of the above tables of Sequential Addressing, with the length being 256 for POWER UP SEQUENCE 1. Apply power and start clock, attempt to maintain CKE = `H' , L(U)DQM = `H' and the other pin are NOP condition at the inputs. 2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 3. Issue precharge commands for all banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue mode register set command to initalize the mode register. Cf.) Sequence of 4 & 5 is regardless of the order. The device is now ready for normal operation. TM Technology Inc. reserves the right P.11 to change products or specifications without notice. Publication Date:AUG. 2004 Revision: A tm Register Refresh TE CH T436416C A13, A12 SIMPLIFIED TRUTH TABLE COMMAND Mode Register Set Auto Refresh Self Refresh Entry Exit H L H H H H H H L H L H H H X CKEn-1 CKEn CS RAS CAS WE DQM H X H L H X X X X X L H L H L L H L L L L L H L X H L H L L H X L H H H L X V X X H X V X L H X H L L H H X V X X H X V H H X H H L L L X V X X H X V X X X X X X X X X X X X V X 7 V X L H X V V V X X Row Address L H L H X Column Address (A0~A7) Column Address (A0~A7) A10/AP A9~A0, Note A11 L L L L X X 1,2 3 3 Bank Active & Row Address Auto Precharge Disable Read Column Auto Precharge Enable Address Write & Column Auto Precharge Disable Auto Precharge Enable Address Burst Stop 4,5 4,5 6 4 Precharge Bank Selection All Banks Entry Exit Entry Clock Suspend or Active Power Down Precharge Power Down Mode DQM No Operation Command Exit H X X X X X L H H H (V=Valid , X=Don't Care , H=Logic High , L=logic Low) Notes : 1. OP Code : Operation Code. A0~A11 , A13~A12 : Program keys.(@MRS) 2. MRS can be issued only at both banks precharge state. A new command can be issued after 2 clock cycle of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by `Auto'. Auto / self refresh can be issued only at both banks precharge state. 4. A13~A12 : Bank select address. If both A13 and A12 are 'Low' : at read , write , row active and precharge , bank A is selected. If both A13 is `Low' and A12 is `High' : at read , write , row active and precharge , bank B is selected. If both A13 is `High' and A12 is `Low' : at read , write , row active and precharge , bank C is selected. If both A13 and A12 are 'High' : at read , write , row active and precharge , bank D is selected If A10/AP is `High' : at row precharge , A13 and A12 ignored and all banks are selected. 5. During burst read or write with auto precharge , new read/write command cannotbeissued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) TM Technology Inc. reserves the right P.12 to change products or specifications without notice. Publication Date: AUG. 2004 Revision: A tm 0 CLOCK CKE TE CH tCH T436416C Single Bit READ-Write Cycle (Same Page) @CAS Latency=3,Burst Length=1 1 2 3 4 tCL 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 tCC HIGH tRAS tRC *Note1 tSH CS tRCD tSH tSS tRP RAS tSS tSH tCCD CAS tSS tSH tSS ADDR Ra tSS *Note2 Ca Cb tSH Cc Rb *Note2. 3 *Note2. 3 *Note2. 3 *Note4 *Note2 A13,A12 Bs Bs Bs Bs Bs Bs A10/AP Ra *Note3 *Note3 *Note3 *Note4 Rb tRAC tSRC tSH DQ tSLZ Qa tOH Db tSS tSH Qc WE tSS tSH DQM tSS Row Active Read Write Read Precharge Row Active :Don't care TM Technology Inc. reserves the right P.13 to change products or specifications without notice. Publication Date: AUG. 2004 Revision: A tm TE CH T436416C *note : 1. All input expect CKE & DQM can be don't care when CS is high at the CLK high going edge. 2. Bank active & read/write are controlled by A13 - A12. A13 0 1 0 1 A12 0 0 1 1 Active & Read/Write Bank A Bnak B Bank C Bnak D 3. Enable and disable auto precharge function are controlled by A10/AP in read/wirte command. A10 0 1 Auto-Precharge Disable (End of burst) Enable (End of burst) A13 0 1 0 1 A12 0 0 1 1 Operation Enable read/write command for bank A . Enable read/write command for bank B . Enable read/write command for bank C . Enable read/write command for bank D . 4. A10/AP and A13~A12 control bank precharge when precharge command is asserted. A10/AP A13 0 0 0 0 1 0 1 0 1 X A12 0 0 1 1 X precharge Bank A Bank B Bank C Bank D All Bamks TMemory Technology Inc. reserves the right to change products or specifications without notice. P.14 Publication Date: AUG. 2004 Revision: A tm 0 C LOC K CKE TE CH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 T436416C 18 19 Power Up Sequence H ig h le v e l is n e c e s s a ry CS tR P RAS SS tR C SS SS tC C D SS SS tR C SS SS CAS SS SS ADDR SS SS SS SS K ey RAa SS SS SS A 1 3 ,A 1 2 SS K ey A 1 0 /A P SS SS SS SS K ey RAa DQ H ig h -Z WE SS SS SS SS DQM H ig h le v e l is n e c e s s a ry P rec h a rg e A ll B a n k s A u to R efresh A u to R e f re sh M o d e R e g is te r S e t (A -B a n k ) R ow A c t iv e :D o n 't c a re TM Technology Inc. reserves the right P.15 to change products or specifications without notice. Publication Date: AUG. 2004 Revision: A tm 0 CLOCK CKE CS TE CH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 T436416C 17 18 19 Read & Write Cycle at Same Bank @Burst Length = 4 H IG H * N o te 1 tRC tR C D RAS * N o te 2 CAS ADDR Ra C a0 Rb C b0 A 1 3 ,A 1 2 A 1 0 /A P Ra tO H Rb CL=2 RAC * N o te 3 Q a0 t tSA C Q a1 tO H Q a2 Q a3 * N o te 4 D b0 D b1 D b2 D b3 tRD L DQ CL=3 * N o te 3 tSH Z Q a0 tSA C Q a1 Q a2 Q a3 * N o te 4 D b0 D b1 D b2 D b3 tRD L tSH Z WE DQM R ow A c tiv e (A B ank) R e a d (A B ank) P rec h a rg e (A B ank) R o w A c tiv e (A -B n a k ) W rite (A B nak) P rec h a rg e (a-B n a k ) : D o n 't c a r e *Note : 1. Minimum row cycle times is requiqed to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clock. 3. Access time from Row active command. Burst can't end in Full Page Mode. TM Technology Inc. reserves the right P.16 to change products or specifications without notice. Publication Date: AUG. 2004 Revision: A tCC*(tRCD+CAS latency-1)+tSAC 4. Output will be Hi-Z after the end of burst.(1,2,4,8 bit burst) tm 0 CLOCK CKE CS TE CH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 T436416C 17 18 19 Page Read & Write Cycle at Same Bank @ Burst Length = 4 H IG H tR C D RAS * N o te 2 tC C D CAS ADDR Ra C a0 C b0 C c0 C d0 A 1 3 ,A 1 2 A 1 0 /A P tRD L CL=2 DQ CL=3 Q a0 Q a1 Q b0 Q b1 Q b2 D c0 D c1 D d0 D d1 tCD L Q a0 Q a1 Q b0 Q b1 D c0 D c1 D d0 D d2 WE * N o te 3 * N o te 1 DQM R o w A c tiv e (A -B n a k ) R e a d (A B nak) R e a d (A B nak) W rite (A B nak) W rite (A B nak) P rec h a rg e (A -B n a k ) : D o n 't c a r e *Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written. 3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. TM Technology Inc. reserves the right P.17 to change products or specifications without notice. Publication Date: AUG. 2004 Revision: A tm 0 CLOCK CKE CS TE CH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 T436416C 17 18 19 Page Read Cycle at Different Bank @ Burst Length = 4 H IG H * N o te 1 RAS * N o te 2 CAS ADDR RAa CAa RBb CBb CAc CBd CAe A 1 3 ,A 1 2 A 1 0 /A P RAa RBb CL=2 DQ CL=3 Q A a0 Q A a1 Q A a2 Q A a3 Q B b0 Q B b1 Q B b2 Q B b3 Q A c0 Q A c1 Q B d0 Q B d1 Q A e0 Q A e1 Q A a0 Q A a1 Q A a2 Q A a3 Q B b0 Q B b1 Q B b2 Q B b3 Q A c0 Q A c1 Q B d0 Q B d1 Q A e0 Q A e1 WE DQM R o w A c tiv e (A -B a n k ) R e a d (A B ank) R o w A c tiv e (B -B a n k ) R e a d (B B ank) R e a d (A B ank) R e a d (B B ank) R e a d (A B ank) P rec h a rg e (A -B a n k ) : D o n 't c a r e *Note : 1. CS can be don't cared when RAS , CAS and WE are high at the clock high going edge. 2. To interrupt a burst resd by row precharge, both the read and the precharge banks must be the same. TM Technology Inc. reserves the right P.18 to change products or specifications without notice. Publication Date: AUG. 2004 Revision: A tm 0 CLO CK CKE TE CH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 T436416C 17 18 19 Page Write cycle at Different Bank @ Burst Length = 4 H IG H CS RAS CAS * N o te 2 ADDR RAa CAa RBb CBb CAc CBd A 1 3 ,A 1 2 A 1 0 /A P RAa RBb DQ D A a0 D A a1 D A a2 D A a3 DBb0 DBb1 DBb2 DBb3 D A c0 D A c1 DBd0 DBd1 tC D L tR D L WE * N o te 1 DQM R o w A c tiv e (A -B a n k ) R o w A c tiv e (B -B a n k ) W rite (A B an k) W rite (B B an k) W rite (A B an k) W rite (B B an k) P re c h a rg e (A -B a n k ) :D o n 't c a re *Note : 1. To interrupt burst write by row precharge, DQM should be asserted to mask invalid input data. 2. To interrupt burst write by row precharge, both the write and the precharge banks must be the same. TM Technology Inc. reserves the right P.19 to change products or specifications without notice. Publication Date: AUG. 2004 Revision: A tm 0 CLOCK CKE CS TE CH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 T436416C 17 18 19 Read & Write Cycle at Different Bank @ Burst Length = 4 H IG H RAS CAS ADDR RAa CAa RBb CBb RAc CAc A 1 3 ,A 1 2 A 1 0 /A P RAa RBb RAc * N o te 1 tC D L CL=2 DQ CL=3 Q A a0 Q A a1 Q A a2 Q A a3 D B b0 D B b1 D B b2 D B b3 Q A c0 Q A c1 Q A c2 Q A a0 Q A a1 Q A a2 Q A a3 D B b0 D B b1 D B b2 D B b3 Q A c0 Q A c1 WE DQM R o w A c tiv e (A -B a n k ) R e a d (A B ank) R o w A c tiv e (B -B a n k ) P rec h a rg e (A -B a n k ) W rite (B B ank) R o w A c tiv e (A -B a n k ) R e a d (A B ank) : D o n 't c a r e *Note : 1. tCDL should be met to complete write. TM Technology Inc. reserves the right P.20 to change products or specifications without notice. Publication Date: AUG. 2004 Revision: A tm 0 CLOCK CKE CS TE CH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 T436416C 17 18 19 Read & Write Cycle with Auto Precharge @ Burst Length = 4 H IG H RAS CAS ADDR Ra Rb Ca Cb A 1 3 ,A 1 2 A 1 0 /A P Ra Rb CL=2 DQ CL=3 Q a0 Q a1 Q a2 Q a3 D b0 D b1 D b2 D b3 Q a0 Q a1 Q a2 Q a3 D b0 D b1 D b2 D b3 WE DQM R o w A c tiv e (A -B a n k ) R o w A c tiv e (B -B a n k ) R e a d w ith A u to p re c h a rg e (A B ank) C L = 2 A u to P re c h a rg e S ta rt P o in t (A -B a n k ) C L = 3 A u to P re c h a rg e S ta rt P o in t (A -B a n k ) W rite w ith A u to P rec h a rg e (B B ank) A u to P re c h a rg e S tart P o in t (A B ank) : D o n 't c a r e *Note : 1. tCDL should be controlled to meet minimum tRAS before internal precharge start. (In the case of Burst Length = 1 & 2) TM Technology Inc. reserves the right P.21 to change products or specifications without notice. Publication Date: AUG. 2004 Revision: A tm 0 CLO CK CKE TE CH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 T436416C 17 18 19 Clock suspension & DQM Operation Cycle @ CAS Latency = 2 ,Burst Length = 4 CS RAS CAS ADDR Ra Ca Cb Cc A 1 3 ,A 1 2 A 1 0 /A P Ra DQ Q a0 Q a1 Q a2 Q a3 tS H Z Q b0 Q b1 tS H Z D c0 D c2 WE * N o te 3 DQM R o w A c tiv e R ead C lo c k S u sp e n sio n R ead R ead Q D M W rite W rite Q D M C lo c k S u sp e n sio n W rite Q D M : D o n 't c a r e *Note 1. DQM is needed to prevent bus contention. TM Technology Inc. reserves the right P.22 to change products or specifications without notice. Publication Date: AUG. 2004 Revision: A tm 0 CLOCK CKE CS TE CH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 T436416C 17 18 19 Read Interrupted by Precharge Command & Read Burst Stop Cycle @ Burst Length=Full Page H IG H RAS CAS ADDR RAa CAa CAb A 1 3 ,A 1 2 A 1 0 /A P RAa * N o te 2 1 1 CL=2 DQ Q A a0 Q A a1 Q A a2 Q A a3 Q A a4 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 2 2 CL=3 Q A a0 Q A a1 Q A a2 Q A a3 Q A a4 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 WE DQM R o w A c tiv e (A -B a n k ) R e a d (A B ank) B u rst S to p R e a d (A B ank) P rec h a rg e (A -B a n k ) : D o n 't c a r e *Note : 1. Burst can't end in full page mode, so auto precharge can't issue. 2. About the valid DQs after burst stop, it is same as the case of RAS interrupt. Both cases are illustrated above timing diagram. See the lable 1,2 on them. But at burst write, burst stop and RAS interrupt should be compared carefully. Refer the timing diagram of `Full Page write burst stop cycle'. 3. Burst stop is valid at every burst length. TM Technology Inc. reserves the right P.23 to change products or specifications without notice. Publication Date: AUG. 2004 Revision: A tm 0 CLOCK CKE TE CH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 T436416C 17 18 19 Write Interrupted by Prechareg Command & Write Burst Stop Cycle @ Burst Length=Full Page H IG H CS RAS CAS ADDR RAa CAa CAb A 1 3 ,A 1 2 A 1 0 /A P RAa tB D L tR D L * N o te 3 DQ D A a0 D A a1 D A a2 D A a3 D A a4 D Ab0 D Ab1 D Ab2 D Ab3 D Ab4 D Ab5 WE DQM R o w A c ti v e (A -B a n k ) W ri te ( A B an k) B u rs t S t o p W ri te ( A B an k) P rec h a rg e (A -B a n k ) :D o n 't c a r e *Note : 1. Burst can't end in full page mode, so auto precharge can't issue. 2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL. DQM at write interrupted by precharge command is needed to prevent invalid write. Input data after Row precharge cycle will be masked internally. 3. Burst stop is valid at every burst length. TM Technology Inc. reserves the right P.24 to change products or specifications without notice. Publication Date: AUG. 2004 Revision: A tm TE CH 0 1 2 3 SS SS *N o te2 T436416C 4 5 6 7 8 9 SS tss tss Active/ Precharge Power Down Mode @ CAS latency = 2, Butsr length = 4 10 11 12 13 14 15 16 17 18 19 C LO C K tss CKE *N o te1 SS *N o te3 CS SS SS SS SS RAS SS SS SS SS CAS SS SS SS SS ADDR SS SS Ra SS SS Ca A 1 3,A 1 2 SS SS SS SS A 1 0/A P SS SS Ra SS SS tSH Z DQ SS SS Q a0 Q a1 Q a2 WE SS SS SS SS DQM SS SS SS SS P rec h a rg e P o w er -D o w n E n try R o w A c tiv e A c tiv e P rec h a rg e P o w er -D o w n P o w er -D o w n E n try E x it R ea d A c tiv e P o w er -D o w n E x it P rec h a rg e :D o n 't care *Note : 1. Both banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least 1CLK+tSS prior to Row active command. 3. Can not violate minimum refresh specification.(64ms) TM Technology Inc. reserves the right P.25 to change products or specifications without notice. Publication Date: AUG. 2004 Revision: A tm 0 CLO CK CKE CS TE CH 1 2 3 * N o te2 T436416C 4 5 6 SS SS *N o te 4 Self Refresh Entry & Exit Cycle 7 8 9 10 11 12 13 SS t R C m in *N o te 1 *N o te 3 14 15 16 17 18 19 SS *N o te 6 SS tSS SS SS SS *N o te 5 RAS SS SS SS SS *N o te 7 CAS SS SS SS SS ADDR SS SS SS SS A 1 3 ,A 1 2 SS SS SS SS A 1 0 /A P SS SS SS SS DQ H i- z SS H i- z SS WE SS SS SS SS DQM SS SS SS SS S e lf R e fre sh E n try S e lf R e fre sh E x it A u to R e fre s h : D o n 't c a r e *Note : TO ENTER SELF REFRESH MODE 1. CS , RAS & CAS with CKE should be low at the same clock cycle. 2. After 1 clock cycle, all the inputs inculding the system clock can be don't care except for CKE. 3. The device remains in self refresh mode as long as CKE stays `Low'. Cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh. TO EXIT SELF REFRESH MODE 4. System clock restart and be stable before returning CKE high. 5. CS starts from high. 6. Minimum tRC is required after CKE going high to complete self refresh exit. 7. Burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh. TM Technology Inc. reserves the right P.26 to change products or specifications without notice. Publication Date: AUG. 2004 Revision: A tm 0 CLOCK CKE TE CH Auto Refresh Cycle 5 6 0 1 2 3 4 5 6 SS T436416C 2 3 4 7 8 9 10 Mode Register Set Cycle 1 H IG H H IG H SS CS * N o te 2 SS tR P C SS SS RAS * N o te 1 CAS SS SS * N o te 3 ADDR K ey K ey SS SS DQ H i-z H i-z SS WE SS SS DQM SS SS M RS N ew C om m and A u to R e fre sh N ew C om m and :D o n 't c a re *Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle. MODE REGISTER SET CYCLE *Note : 1. CS , RAS , CAS & WE activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table. TM Technology Inc. reserves the right P.27 to change products or specifications without notice. Publication Date: AUG. 2004 Revision: A tm 54 TE CH T436416C PACKAGE DIMENSIONS 54 LEAD TSOP-II (400 mil) D 28 A A2 E1 E A1 1 27 C B1 B Symbol A A1 A2 B B1 C D E E1 Dimension in mm Min Nom Max 1.2 0.4 0.5 0.6 0.15 0.24 0.32 0.40 0.8 0.05 0.10 0.15 22.12 22.22 22.62 11.56 11.76 11.96 10.06 10.16 10.26 0 8 Dimension in inch Min Nom Max 0.047 0.016 0.020 0.024 0.006 0.009 0.012 0.016 0.0315 0.002 0.004 0.006 0.871 0.875 0.905 0.455 0.463 0.471 0.396 0.400 0.404 0 8 TM Technology Inc. reserves the right P.28 to change products or specifications without notice. Publication Date: AUG. 2004 Revision: A |
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